Overview

Best Verification Throughput for Pre-Silicon Verification and Debug

Cadence Palladium emulation platforms provide early hardware/software co-verification and debug and in-circuit emulation. They provide the highest debug productivity early in the design cycle when the RTL is still changing.

Key Benefits

Delivering increased performance, capacity, and debug for the development of complex SoCs and systems

High Performance

1.5X faster performance over Palladium Z2

Large and Scalable Capacity

Provides capacity and scales for multi-billion-gate designs

Fast Compile Times

Modular compiler accelerates compile times – 3 turns per day for billion-gate class designs

High-Performance Debug

At-speed triggers without recompile for faster, easier, more in-depth debug

Use Models

Increase Productivity with Palladium Platform Across Various Use Models

  • Code and functional coverage dump
  • Hardware verification language-based testbench acceleration
  • In-circuit emulation and In-circuit acceleration
  • Hybrid acceleration with virtual platform
  • Universal Verification Methodology (UVM) acceleration
  • Multi-power domain verification with IEEE 1801 UPF constraints
  • Hardware-based and post-process-based massively parallel dynamic power analysis (DPA)
  • Four-state emulation
  • Real number modeling emulation

Offerings

A Full Range of Offerings

Palladium Z3 Enterprise Emulation Platform

  • Scales to 48B gates
  • Modular compiler: Compiles in under 8 hours
  • 1.5X performance over Palladium Z2 system
  • Software compatibility between Palladium Z2 and Palladium Z3 systems
  • Common front-end for all Palladium and Protium systems
  • Common virtual and physical interfaces with Palladium and Protium systems
  • Easy transition from previous-generation Palladium systems

Palladium Z2 Enterprise Emulation Platform

  • 2X capacity, 1.5X performance over Palladium Z1 platform
  • Modular compiler: compiles in under 8 hours
  • 10X faster waveform dump and 2X debug trace depth, 2X faster memory dump and debug upload, and 3X throughput bandwidth to the host
  • FullVision 3.0 – new and improved high-performance debug engine
  • Scalability from 8 million gates to 1152 million gates per racks

Palladium Hybrid

The Helium Virtual and Hybrid Studio extends our emulation and prototyping systems by integrating virtual hybrid models with RTL in Palladium and Protium systems to increase effective performance, add capability, or improve effectiveness in selected use cases.

  • Increase effective performance by offloading already validated performance gating components such as third-party CPU cores
  • Enable system-level verification early by integrating virtual platform models of components still under development
  • Improve effectiveness with system-level testing at unit-level capacity by integrating a single RTL with a system-level virtual platform

Apps

  • 4-State Emulation App: Enables the acceleration of simulations requiring X-propagation and verification of multiple switched power domains
  • Real Number Modeling App: Enables the acceleration of simulations on mixed-signal designs.
  • Dynamic Power Analysis App: A very fast, massively parallel architecture for power analysis supporting multi-billion gate SoCs and millions of clocks
  • Job Scheduling App: An enterprise-scale flexible queue-based interface for dispatching emulation jobs supporting job prioritization and job starvation mitigation
  • Safety App: Serial fault emulation, which combines with the Cadence Digital Safety Verification, to enable the highest performance safety campaign execution for ISO 26262 compliance
  • Video Analyzer App: A graphical view of graphical and video-based interfaces with a live view of real-time data supporting capture, debug, analysis, and playback of waveform data

Interfaces

  • Accelerated VIP and VirtualBridge Adapters: High-performance protocol IP that enables virtual driver- and application-level testing with the Palladium and Protium systems
  • Memory Model Portfolio: Industry-standard memory models for easy integration with the Palladium and Protium systems
  • Protium Daughtercards: Integrated ICE interfaces, external memory solutions, test equipment adapters, and debug with external data capture cards (DCC)
  • SpeedBridge Adapters and EDKs: Protocol interface solutions that enable efficient driver- and application-level testing and off-the-shelf, BIOS-optimized target hosts to enable integrated, unmodified OS and software
  • Virtual Debug and Physical JTAG: Enables users of third-party debuggers, including Lauterbach Trace32, Xtensa OCD, Arm Development Studio, Green Hills MULTI, and Open OCD, to access Palladium or Protium emulated processor cores via JTAG, DAP, and AMBA protocols

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